Semiconductor constructions, and methods of forming semiconductor constructions

ABSTRACT

The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1×10 17  atoms/cm 3  with n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.

TECHNICAL FIELD

[0001] The invention pertains to semiconductor constructions and methodsof forming semiconductor constructions. In particular aspects, theinvention pertains to isolation region constructions which can beutilized for, for example, electrically isolating transistorconstructions from one another.

BACKGROUND OF THE INVENTION

[0002] Electrical isolation is commonly utilized in semiconductorconstructions to alleviate, or prevent, leakage between electricaldevices. For instance, it is frequently desired in dynamic random accessmemory (DRAM) fabrication to avoid sub-threshold leakage between accessdevices (such as, for example, access transistor constructions). Therecan be several facets which influence leakage currents between fieldeffect transistor devices, including, for example, junction leakage insource/drain regions; drain-induced barrier lowering (DIBL) due to shortgate lengths; gate-induced drain leakage (GIDL) due to high electricfields in a gate overlap region; narrow-width effects; andstress-induced leakage current (SILC) due to a proximity of an isolationregion to a device.

[0003] A ratio of I_(on) (drive current) to I_(off) (sub-thresholdleakage) can be utilized as a figure of merit for determining if accessdevices are performing adequately. It is found that reducing gate oxidethickness of access devices can improve a sub-threshold behavior of thedevices while simultaneously increasing a drive current. However, athreshold voltage of a device reduces with the decrease in gate oxidethickness. Increasing dopant levels in channels of the devices canincrease the threshold voltage to an acceptable level and compensate forthe reduction in gate oxide thickness, but can increase junction leakagein source/drain regions. Additionally, the increased dopant level in achannel of a device can adversely cause junction capacitance toincrease, and reduce the current drive of the device.

[0004] It would be desirable to develop new methods for reducingsub-threshold leakage of devices. It would be further desirable if suchnew methods avoided increasing dopant concentration in channel regionsof access devices. Additionally, it would be desirable if such newmethods could be utilized for forming structures suitable for electricalisolation in an integrated circuit construction.

SUMMARY OF THE INVENTION

[0005] In one aspect, the invention encompasses a semiconductorconstruction which includes a gate layer over a segment of a substrate.The segment can be considered a channel region. The gate layer has afirst type majority dopant therein. A pair of conductively-dopeddiffusion regions are within the substrate adjacent the channel region,and spaced from one another by the channel region. Theconductively-doped diffusion regions have a second type majority dopanttherein. The majority dopant of the conductively-doped diffusion regionsis opposite to the majority dopant of the gate layer. In other words,one of the first and second type dopants is n-type, and the other isp-type. The gate layer can, in particular applications, be electricallyconnected to a ground associated with the substrate.

[0006] In one aspect, the invention encompasses a DRAM array having oneor more structures therein which include a gate layer separated from asilicon-containing substrate by an intervening insulative material. Thegate layer is doped to at least 1×10¹⁷ atoms/cm³ with n-type dopant andis also doped to at least 1×10¹⁷ atoms/cm³ with p-type dopant.

[0007] The invention also encompasses methods of forming semiconductorconstructions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0009]FIG. 1 is a diagrammatic, cross-sectional view of a pair offragments of a semiconductor wafer construction which can be formed inparticular embodiments of the present invention.

[0010]FIG. 2 is a diagrammatic, cross-sectional view of a pair offragments of a semiconductor wafer construction at a preliminary stageof a fabrication sequence which can be utilized in forming the FIG. 1structures.

[0011]FIG. 3 is a view of the FIG. 2 wafer fragments shown at aprocessing stage subsequent to that of FIG. 2.

[0012]FIG. 4 is a view of the FIG. 2 fragments shown at a processingstage subsequent to that of FIG. 3.

[0013]FIG. 5 is a view of the FIG. 2 fragments shown at a processingstage subsequent to that of FIG. 4.

[0014]FIG. 6 is a view of the FIG. 2 fragments shown at a processingstage subsequent to that of FIG. 5.

[0015]FIG. 7 is a diagrammatic, cross-sectional view of a semiconductorwafer fragment shown at a preliminary step of another processingsequence encompassed by particular aspects of the present invention.

[0016]FIG. 8 is a view of the FIG. 7 fragment shown at a processing stepsubsequent to that of FIG. 7.

[0017]FIG. 9 is a view of the FIG. 7 fragment shown at a processing stepsubsequent to that of FIG. 8.

[0018]FIG. 10 is a view of the FIG. 7 fragment shown at a processingstep subsequent to that of FIG. 9.

[0019]FIG. 11 is a view of the FIG. 7 fragment shown at a processingstep subsequent to that of FIG. 10.

[0020]FIG. 12 is a view of the FIG. 7 fragment shown at a processingstep subsequent to that of FIG. 11.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021]FIG. 1 illustrates a semiconductor construction 10 encompassed byparticular aspects of the present invention. Construction 10 includes apair of fragments 12 and 14. Fragments 12 and 14 comprise a substrate 16which can comprise, consist essentially of, or consist ofmonocrystalline silicon, and such monocrystalline silicon can belightly-doped with one or more suitable dopants. To aid ininterpretation of the claims that follow, the terms “semiconductivesubstrate” and “semiconductor substrate” are defined to mean anyconstruction comprising semiconductive material, including, but notlimited to, bulk semiconductive materials such as a semiconductive wafer(either alone or in assemblies comprising other materials thereon), andsemiconductive material layers (either alone or in assemblies comprisingother materials). The term “substrate” refers to any supportingstructure, including, but not limited to, the semiconductive substratesdescribed above.

[0022] In particular aspects, fragment 14 can correspond to a DRAMarray, and fragment 12 can correspond to a portion of a waferconstruction peripheral to the DRAM array. Referring initially tofragment 14, such comprises a plurality of field effect transistordevices 18, 20, 22 and 24 supported by substrate 16, and also comprisesa device 52 having a different threshold voltage than devices 18, 20, 22and 24. Device 52 can be utilized for electrically isolating devices 20and 22 from one another, as discussed below.

[0023] Each of devices 18, 20, 22 and 24 comprises a transistor gatestack 26 which includes an insulative material 28, a conductively-dopedsemiconductor material 30 (also referred to as a gate layer), anelectrically conductive mass 32, and an insulative cap 34.

[0024] Insulative material 28 can comprise, for example, one or more ofsilicon nitride, silicon dioxide and silicon oxynitride. Insulativematerial 28 typically comprises silicon dioxide, and can be referred toas gate oxide.

[0025] Conductively-doped material 30 can comprise, for example,conductively-doped silicon. The silicon is typically in an amorphousand/or polycrystalline form. The dopant can comprise n-type dopant (suchas, for example, phosphorous or arsenic), or can comprise p-type dopant(such as, for example, boron).

[0026] Conductive mass 32 will typically comprise a layer of silicideformed directly on an upper surface of a silicon material 30; or a layerof metal formed directly on (i.e., physically against) a barrier layerof WN_(x) or TiN, which in turn is on the silicon material 30.

[0027] Insulative cap 34 can comprise, for example, one or both ofsilicon nitride and silicon dioxide.

[0028] The gate stacks comprise sidewalls, and electrically insulativespacers 40 are formed along such sidewalls. Spacers 40 can comprise, forexample, silicon nitride, and can be formed by depositing a materialconformally over substrate 16 and gate stacks 26, and subsequentlyanisotropically etching such material.

[0029] A plurality of source/drain regions 42 are provided withinsubstrate 16 and between gate stacks 26. The gate stacks 26 can beconsidered as being directly over segments of substrate 16, andsource/drain regions 42 can be considered as being spaced from oneanother by at least portions of such segments. In the shownconstructions, source/drain regions 42 extend partially under gatestacks 26.

[0030] Source/drain regions 42 are conductively-doped diffusion regionsextending into substrate 16. Typically, each of transistor constructions18, 20, 22 and 24 will be an NMOS transistor, and accordinglysource/drain regions 42 will be n-type doped diffusion regions. In otherwords, the majority dopant within regions 42 will be n-type dopant. Theterm “majority dopant” refers to the dopant that is most abundant withinthe regions. Accordingly, if both p-type dopant and n-type dopant arepresent in the regions, the majority dopant type will be that which ismost prevalent. Additionally, it is noted that a stack 52 (discussed inmore detail below) provided between stacks 26 can be incorporated intoan NMOS transistor if a sufficient threshold voltage is provided.

[0031] The source/drain regions 42 extend under spacers 40 in the shownconstruction. It is to be understood, however, that other structures canbe formed in which the source/drain regions do not extend underneath thespacers, or even in which at least some of the spacers are eliminated.

[0032] The various source/drain regions are connected to eithercapacitor constructions 44 or digit lines 46 to define various memorycell units of the DRAM memory array.

[0033] An isolation region 50 extends between transistor constructions20 and 22, and can be utilized to electrically isolate such transistorconstructions from one another. Isolation region 50 comprises the stack52 similar to the stacks 26 of gate constructions 18, 20, 22 and 24.Stack 52 comprises the insulative material 28, conductive mass 32, andinsulative cap 34 utilized in gate stacks 26. However, stack 52 differsfrom the gate stacks in having a heavily doped material 54 which isdifferently doped than the material 30 of stacks 26.

[0034] In particular aspects, material 54 can comprise silicon dopedwith significant concentrations of an opposite type dopant as thatprimarily utilized in source/drain regions 42. For instance, ifsource/drain regions 42 primarily comprise n-type dopant, material 54can primarily comprise p-type dopant. The utilization of p-type dopantas a majority dopant within doped gate layer 54, while havingsource/drain regions 42 with n-type dopant as majority dopant, can causestack 52 to have a high threshold voltage relative to adjacent devices.This can enable stack 52 to function primarily as an isolation region atparticular threshold voltages utilized to drive adjacent devices, ratherthan as a transistor construction.

[0035] In some aspects of the invention material 54 can comprisesignificant concentrations of both p-type and n-type dopant, and can,for example, comprise concentrations of from 1×10¹⁸ atoms/cm³ to 5×10²¹atoms/cm³ of both p-type and n-type dopants. Typically a concentrationof the dopants is about 1×10²⁰ atoms/cm³.

[0036] If stack 52 is utilized as an isolation region, it can bedescribed as an isolation region having a mass 54 of material extendingbetween a pair of adjacent source/drain regions 42. Further, theadjacent source/drain regions can, as shown, extend under the gateelectrode (i.e., can extend under mass 54).

[0037] Stack 52 is shown having conductive layer 32 in contact withother electrical circuitry 56. In embodiments in which stack 52 isutilized as an isolation region, the other circuitry 56 can be anelectrical ground associated with construction 10, or can be slightlypositive or negative relative to ground as long as device 52 does notturn on an underlying channel.

[0038] It is noted that stack 52 can be utilized for other applicationsbesides an isolation region, and in such other applications electricalcircuitry 56 can be at an electrical potential other than ground andconfigured to turn on the channel under device 52.

[0039] As a result of the dopant variation within layer 54 (relative tothe layers 30 of gate stacks 26) the apparent or effective thickness ofgate oxide 28 within stack 52 can change relative to that of stacks 26.In other words, even though gate oxide 28 has the same physicalthickness in stacks 26 and stack 52, the effective electrical thicknessof the gate oxide will be increased in stack 52 relative to stacks 26.Various alterations in stack 52 can be utilized to enhance the effect onthe electrical thickness of oxide 28, including, for example, dopantdepletion in the silicon layer 54 close to or at a gate oxide 28/siliconlayer 54 interface; a change in the insulative material 28 to alter adielectric constant of such material; and/or quantization in aninversion layer close to a gate oxide 28/silicon 54 interface. Dopantvariation within layer 54 can also soften gate induced drain leakageeffects relative to source/drain regions proximate layer 54.

[0040] In particular aspects of the present invention, there is aneffective dopant depletion relative to an interface between gate oxide28 and silicon layer 54. Specifically, silicon layer 54 has a lowereffective concentration of n-type dopant than do the silicon layers 30.Such can be accomplished by initially providing layer 54 to have thesame n-type dopant concentration as do layers 30, and then subsequentlyadding sufficient p-type dopant to layer 54 to alter electricalproperties of layer 54. The p-type dopant concentration can besufficient to overwhelm the n-type dopant concentration (i.e., to formthe p-type dopant as the majority dopant in layer 54), or alternativelycan be sufficient simply to have a measurable effect on the workfunction of a transistor construction comprising stack 52.

[0041] The alteration of layer 54 relative to layers 30 can render adevice comprising stack 52 to be a special device relative to thedevices comprising stacks 26. In particular aspects, such special devicecan be utilized as an electrical insulator between adjacent stacks. Inother aspects, such special device can be utilized to drive capacitorsor other electrical components under particular operating conditions.

[0042] A possible mechanism by which dopant depletion in asilicon-containing layer 54 can alter a work function of a deviceincorporating stack 52 is as follows. First, it is noted that variousheat steps can be utilized to activate dopants and formdegenerately-doped polysilicon films (with the term “degenerately-doped”referring to a fermi level close to or inside of a conduction band ofsilicon for n-type doped silicon). If the silicon layer is less thandegenerately-doped, low frequency CV characteristics can occur withreduced gate capacitance (i.e., less than maximum oxide capacitance)when the gate is biased positive. This can be caused by depletion ofmajority carriers (electrons) near a silicon/gate oxide interface. Suchdepletion of carriers can be considered to be electrically equivalent tocreation of a resistive layer at the interface, or in other words, anincrease in gate oxide thickness. The mechanism is provided herein toassist the reader in understanding the invention, and is not to beconstrued as limiting the claims except to the extent, if any, that themechanism is expressly recited in the claims.

[0043] Referring next to the fragment 12 of construction 10, suchcomprises a transistor structure 60 which includes a gate stack 62 andsource/drain regions 64. Gate stack 62 comprises gate oxide 28,conductive mass 32, insulative cap 34, and sidewall spacers 40.Insulative material 28, conductive mass 32, and insulative cap 34 can beidentical to the structures having the same numeric labels describedwith reference to fragment 14. Additionally, gate 62 comprises aconductively-doped material 66, which can be, for example, either n-typeor p-type-doped silicon. In particular aspects, construction 60 cancomprise a layer 66 which is majority-doped with p-type dopant, andsource/drain regions 64 can also comprise p-type dopant as a majoritydopant.

[0044] In particular aspects of the invention, a difference betweenstack 52, and stacks 18, 20, 22, 24 and 62 of fragments 12 and 14 can bethat stack 52 is an isolation region in which conductive material 32 andconductively-doped silicon 54 are electrically connected to ground. Insuch applications, another distinction can be that stack 52 comprises aconductively-doped material 54 (typically silicon) which has a differenttype majority dopant than do the source/drain regions 42 immediatelyadjacent stack 52. For instance, source/drain regions 42 can comprisen-type dopant as a majority dopant, and material 54 can comprise p-typedopant as a majority dopant. Such would be a typical arrangement inapplications in which stack 52 is utilized as an isolation structureformed within a DRAM array. It should be understood, however, that theinvention can also encompass applications in which the majority dopantof source/drain regions 42 is p-type and the majority dopant of material54 is n-type. The arrangement in which source/drain regions 42 arep-type and material 54 is majority doped with n-type dopant can beutilized in constructions in which stack 52 is incorporated as part of atransistor construction.

[0045] In various applications, material 54 can comprise essentially onetype of dopant (i.e., at least 99% of the dopant within material 54 canbe either n-type or p-type) or material 54 can effectively comprise twotypes of dopant (in other words, less than 99% of the dopant withinmaterial 54 is either n-type or p-type). In particular applications,material 54 can be doped with p-type dopant and be utilized as anisolation region in a DRAM array.

[0046] In the shown construction, material 54 is physically againstinsulative mass 28, and conductive mass 32 is physically againstmaterial 54. Further, conductive mass 32 can comprise a silicide layerwhich is formed directly on (physically against) layer 52, and canfurther comprise a metal layer, metal compound layer, and/or metal alloylayer which is formed over and physically against the silicide layer.

[0047] Stack 52 can be considered to be within a DRAM array, and thearray can be, for example, from 4F² to 8F².

[0048] A method of forming the construction of FIG. 1 is described withreference to FIGS. 2-6. In describing FIGS. 2-6, similar numbering willbe used as was utilized above in describing FIG. 1, as appropriate.

[0049] Referring initially to FIG. 2, wafer construction 10 is shown ata preliminary processing stage. Construction 10 comprises substrate 16,insulative layer 28, and a mass 100. Mass 100 can be undoped asinitially deposited, or alternatively can be in situ doped. In the shownapplication, mass 100 is undoped, and accordingly has not acquired theproperties of either mass 66 (FIG. 1), mass 30 (FIG. 1), or mass 54(FIG. 1).

[0050] A masking material 102 is formed over mass 100, and such blocksportions of mass 100. Masking material 102 can comprise, for example,photoresist; and can be patterned utilizing suitable photolithographicprocesses.

[0051] A dopant 104 is implanted relative to construction 10, and formsthreshold voltage implant regions 106 for a DRAM array which willultimately be formed relative to fragment 14. Masking layer 102 preventsthe dopant from being implanted into the blocked regions of fragment 12and 14. The blocked region of fragment 14 corresponds to a region wherestack 52 (FIG. 1) is ultimately to be formed. It is to be understood,however, that in other various applications of the invention some or allof the shown portions of masking material 102 can be eliminated. In suchapplications, the threshold voltage implant can extend across anentirety of fragment 14 and/or can extend across a portion or anentirety of fragment 12.

[0052] Referring to FIG. 3, a second dopant 110 is implanted intoexposed portions of mass 100 to convert such exposed portions to dopedmaterial 30. Dopant 110 can comprise, for example, n-type dopant (suchas phosphorous or arsenic). Dopant 110 can be provided to aconcentration of at least 1×10²⁰ atoms/cm³, and typically is provided toa concentration of from about 1×10²⁰ atoms/cm³ to about 5×10²¹atoms/cm³. In applications in which masking material 102 is not utilizedduring formation of threshold voltage implants 106 (the stage shown withreference to FIG. 2), the masking material would typically still beprovided prior to the shown processing of FIG. 3 to block at least someof fragment 12, as well as blocking a portion of fragment 14 where stack52 (FIG. 1) is ultimately to be formed.

[0053] Referring to FIG. 4, masking material 102 (FIG. 3) is removed andreplaced by another patterned masking material 112. Masking material 112can comprise, for example, photoresist, and can be formed into the shownpattern by, for example, photolithographic processing. Masking material112 covers some portions of fragment 14 while leaving a portion wherestack 52 is ultimately to be formed uncovered; and leaves the shownportion of fragment 12 uncovered.

[0054] A dopant 114 is implanted into construction 10, and specificallyis implanted into portions of material 100 (FIG. 3) which are notcovered by mask 112. Such converts the material to material 66 relativeto fragment 12, and to material 54 relative to fragment 14. Dopant 114can comprise an opposite conductivity type relative to dopant 110.Accordingly, if dopant 110 is n-type, dopant 114 can be p-type. Further,dopant 114 can be implanted to a concentration comparable to that ofdopant 110 (specifically, to a concentration greater than 1×10²⁰atoms/cm³).

[0055] In particular applications, mask 102 (FIG. 3) can be eliminated,and dopant 110 implanted into an entirety of material 100 (FIG. 2).Subsequently, mask 112 can be formed and dopant 114 implanted at aconcentration higher than that of dopant 110. The dopant 114 can theneffectively overwhelm the dopant 110 within exposed (unblocked) regionsof fragments 12 and 14 to form the doped materials 54 and 66.

[0056] In particular applications, the portion of fragment 12 exposed todopant 114 corresponds to a region where a gate of a PMOS transistorwill be formed, and the exposed portion of material 100 (FIG. 2) infragment 14 corresponds to a portion where an isolation structure 52(FIG. 1) will ultimately be formed. Accordingly, dopant 114 can besimultaneously implanted into a portion of the stack corresponding to anisolation structure to be formed within a DRAM array and a portion ofthe gate stack corresponding to a PMOS transistor in a region peripheralto the DRAM array.

[0057] Referring to FIG. 5, layers 32 and 34 are formed across fragments12 and 14. As discussed above, layer 32 can comprise silicide, metal,metal compounds and/or metal alloys; and layer 34 can comprise aninsulative material, such as, for example, silicon dioxide and/orsilicon nitride.

[0058] Referring to FIG. 6, stacks 26, 52 and 62 are patterned from thelayers 28, 30, 32, 34, 54 and 66 of FIG. 5. Such patterning can beaccomplished by, for example, forming a patterned photoresist mask (notshown) over the layers, and subsequently transferring a pattern from themask through the layers utilizing suitable etching conditions.

[0059] The stacks 26, 52 and 62 can be incorporated into theconstructions of FIG. 1 by forming source/drain regions 42 and 64 (shownin FIG. 1) within substrate 16, and by forming the sidewall spacers 40(shown in FIG. 1).

[0060] In particular aspects of the invention, the silicon mass 66 inperipheral array 12 can be more heavily doped than the material 30 ofthe stacks 26 within DRAM array 14. Further, the peripheral region canbe doped simultaneously with various processing occurring in the arrayregion in addition to, or alternatively to, that shown. For instance,the silicon 66 can be doped during implant of a threshold voltage adjustin the array.

[0061] Another application of the invention is described with referenceto FIGS. 7-12. In referring to FIGS. 7-12, the DRAM array fragment(fragment 14 of FIGS. 1-6) is the only portion of construction 10 whichis illustrated. Similar numbering will be utilized in describing FIGS.7-12 as was used above in describing FIGS. 1-6, where appropriate.

[0062] Referring initially to FIG. 7, fragment 14 is illustrated at apreliminary stage. The fragment comprises semiconductor substrate 16,having insulative material layer 28 and material 100 formed thereover. Afirst dopant 104 is implanted through layers 28 and 100, and forms athreshold voltage implant 106 within substrate 16. Dopant 104 cancomprise, for example, boron, indium, BF₂, and/or B₁₀H; and can beformed to a concentration of, for example, from 5×10¹⁶ atoms/cm³ to1×10¹⁸ atoms/cm³ within threshold voltage region 106.

[0063] Referring to FIG. 8, a second dopant 110 is implanted into thematerial 100 (FIG. 7) to convert the material into a doped material 30.Second dopant 110 can comprise, for example, n-type dopant. It is notedthat the order of implant of dopants 104 and 110 can be reversed fromthe order shown. It is also noted the material can be initially formedto be situ doped, and the processing of FIG. 8 omitted.

[0064] Referring to FIG. 9, a masking material 200 is formed over dopedmaterial 30 and patterned to leave a portion of material 30 exposed.Subsequently, a dopant 114 is implanted into construction 10, andspecifically into the exposed portion of the material to convert thematerial to a portion 54 having a different dopant composition than doesthe remainder of the doped material. Dopant 114 can comprise, forexample, p-type dopant, and can be implanted to a concentrationsufficient to cause material 54 to have measurably different electricalperformance aspects than do other portions of material 30. Dopant 114can, in other words, have an opposite conductivity type than does thedopant 110 initially provided within the doped material. Accordingly, ifdopant 110 comprises n-type dopant, then dopant 114 can comprise p-typedopant, and vice versa. Dopant 114 can be provided to a suitableconcentration to overwhelm the initially provided dopant 110, andaccordingly to change the majority dopant within region 54 to bedifferent than the majority dopant within the other portions of dopedmaterial 30.

[0065] Referring to FIG. 10, mask 200 (FIG. 9) is removed, andsubsequently layers 32 and 34 are formed.

[0066] Referring to FIG. 11, stacks 26 and 52 are patterned from layers28, 30, 32, 34 and 54. Such patterning can be accomplished using similarprocessing to that described above with reference to FIG. 6.

[0067] Referring to FIG. 12, source/drain regions 42 are formed, andspacers 40 are also formed. Subsequently, bitline contacts (not shown inFIG. 12) and capacitor contacts (not shown in FIG. 12) can be formed tocomplete the DRAM array construction illustrated in FIG. 1.

[0068] The inclusion of two types of dopant in mass 54 can create asignificant shift in a threshold voltage of a device incorporating stack52 relative to transistor devices incorporating stacks 26. A shift canbe at least about 400 millivolts relative to a heavily doped siliconmaterial (with heavily doped being a silicon having from 1×10²⁰ to about1×10²¹ atoms/cm³). Even if there is an order of magnitude reduction inthe amount of dopant in the silicon, the shift in the threshold voltagecan be comparable. Further, even a relatively small amount of depletion(i.e. inclusion of p-type dopant in an otherwise n-type dopedsemiconductive layer) can significantly shift a threshold voltage of adevice incorporating the layer. A small amount of depletion can be lessthan 10%, and in particular aspects being from about 5 to about 7%, withan exemplary depletion amount being about 6.5%.

[0069] There can be several advantages to utilization of methodology ofthe present invention as opposed to physically growing thicker gateoxides within various stacks of a DRAM array. For instance, themethodology of the present invention can enable sub-thresholdcharacteristics of a device to be retained or improved while increasingelectrical gate oxide thickness in an inversion region of the device.Further, less of a channel (threshold voltage-adjust) implant can beutilized to target a given threshold voltage for a device. Additionally,there can be an improvement in junction leakage characteristics on astorage node side of a device, or in other words, there can be animproved static refresh characteristic of the device.

[0070] It can be desirable to fabricate the stack 52 so that dopants donot reach an interface between material 54 and insulative material 28 toavoid what could otherwise be a large impact on refresh of devicesincorporating stack 52.

[0071] In applications in which stack 52 is utilized solely as anisolation device, the counter-dopant level within material 54 can beprovided by a boron implant with a dose of from 5×10¹⁴/cm² to 5×10¹⁵/cm²and energy of from 1 KeV to 4 keV. The boron implant can createdepletion within material 54 which effectively increases an electricalgate oxide thickness associated with stack 52. It is possible that boronmay flow through an oxide insulative material 28 and into an active areabeneath stack 52. This could actually be a benefit, since it would allowan increase in a surface concentration of p-type dopant of an insulativestructure associated with stack 52 without significant risk of thep-type dopant (for example boron) migrating to a storage node diode andcausing increased diode leakage.

[0072] If the device 50 of FIG. 1 is utilized solely for an isolationdevice, and if doped material 54 has an opposite-type majority dopantrelative to source/drain regions 42, a threshold voltage of the devicecan be increased by about 1 volt without implanting p-type dopant into achannel region beneath stack 52. If a threshold voltage differencebetween the device 50 and proximate devices is desired to be less than 1volt, a partial channel implant can be provided for device 50 relativeto full channel implants for the devices proximate device 50.

[0073] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor construction comprising a DRAM array having one ormore structures therein which include a first conductively-dopedmaterial separated from a second conductively-doped material by anintervening insulative material; the first conductively-doped materialbeing doped to at least 1×10¹⁷ atoms/cm³ with n-type dopant and to atleast 1×10¹⁷ atom s/cm³ with p-type dopant.
 2. The semiconductorconstruction of claim 1 wherein the first conductively-doped materialcomprises silicon.
 3. The semiconductor construction of claim 1 whereinthe second conductively-doped material comprises silicon.
 4. Thesemiconductor construction of claim 1 wherein the firstconductively-doped material comprises silicon, and wherein the secondconductively-doped material comprises monocrystalline silicon.
 5. Thesemiconductor construction of claim 1 wherein a majority dopant in thefirst conductively-doped material is n-type.
 6. The semiconductorconstruction of claim 1 wherein a majority dopant in the firstconductively-doped material is p-type.
 7. The semiconductor constructionof claim 1 wherein the DRAM array comprises a pair of transistorconstructions separated from one another by at least one of thestructures comprising the first conductively-doped material; the atleast one of the structures electrically isolating the transistorconstructions from one another.
 8. The semiconductor construction ofclaim 1 wherein the DRAM array comprises a pair of transistorconstructions separated one another by one of the structures comprisingthe first conductively-doped material; the one of the structureselectrically isolating the transistor constructions from one another. 9.A semiconductor construction comprising: a semiconductive materialsubstrate supporting an electrical ground; a conductively-dopedsemiconductive material directly over a segment of the semiconductivematerial substrate, the conductively-doped semiconductive materialhaving a first type majority dopant therein and being electricallyconnected with the ground; and a pair of conductively-doped diffusionregions within the semiconductive material substrate adjacent thesegment and spaced from one another by at least a portion of thesegment; the conductively-doped diffusion regions having a second typemajority dopant therein; one of the first and second types being n-typeand the other being p-type.
 10. The semiconductor construction of claim9 wherein the first type is n-type.
 11. The semiconductor constructionof claim 9 wherein the first type is p-type.
 12. The semiconductorconstruction of claim 9 wherein more than 99% of the dopant in the dopedsemiconductive material is the first type; and wherein the first type isn-type.
 13. The semiconductor construction of claim 9 wherein more than99% of the dopant in the doped semiconductive material is the firsttype; and wherein the first type is p-type.
 14. The semiconductorconstruction of claim 9 wherein less than 99% of the dopant in the dopedsemiconductive material is the first type; and wherein the first type isn-type.
 15. The semiconductor construction of claim 9 wherein less than99% of the dopant in the doped semiconductive material is the firsttype; and wherein the first type is p-type.
 16. The semiconductorconstruction of claim 9 wherein the semiconductive material of thesemiconductive material substrate comprises monocrystalline silicon. 17.The semiconductor construction of claim 9 further comprising aninsulative material between the substrate and the conductively-dopedsemiconductive material.
 18. The semiconductor construction of claim 17wherein the insulative material comprises silicon dioxide.
 19. Thesemiconductor construction of claim 17 wherein the conductively-dopedsemiconductive material is physically against the insulative material.20. The semiconductor construction of claim 9 wherein theconductively-doped semiconductive material comprises dopedpolycrystalline silicon.
 21. The semiconductor construction of claim 9wherein the conductively-doped semiconductive material comprises dopedpolycrystalline silicon, and further comprising a silicide layer overand physically against the doped polycrystalline silicon.
 22. Thesemiconductor construction of claim 9 wherein the doped semiconductivematerial has a shape comprising a pair of opposing sidewalls; theconstruction further comprising a pair of spacers along the opposingsidewalls; the conductively-doped diffusion regions extending under thespacers.
 23. A semiconductor construction comprising a pair oftransistor constructions separated by an isolation region whichelectrically isolates the transistor constructions from one another, andwherein: each of the transistor constructions comprises a transistorgate between a pair of source/drain regions; the transistor gatescomprising a first semiconductive material conductively doped to a firstdopant type; and the source/drain regions comprising a secondsemiconductive material conductively doped to the first dopant type; theisolation region comprises a mass between two of the source/drainregions; the isolation region mass comprising the first semiconductivematerial conductively doped to a second dopant type; and one of thefirst and second dopant types is n-type and the other is p-type.
 24. Thesemiconductor construction of claim 23 wherein the two of thesource/drain regions extend under the mass.
 25. The semiconductorconstruction of claim 23 wherein the transistor gates and isolationregion mass are over a monocrystalline silicon substrate.
 26. Thesemiconductor construction of claim 23 wherein the first type is n-type.27. The semiconductor construction of claim 23 wherein the first type isp-type.
 28. The semiconductor construction of claim 23 wherein more than99% of the dopant in the isolation region is the second dopant type; andwherein the second dopant type is n-type.
 29. The semiconductorconstruction of claim 23 wherein more than 99% of the dopant in theisolation region is the second dopant type; and wherein the seconddopant type is p-type.
 30. The semiconductor construction of claim 23wherein less than 99% of the dopant in the isolation region is thesecond dopant type; and wherein the second dopant type is n-type. 31.The semiconductor construction of claim 23 wherein less than 99% of thedopant in the isolation region is the second dopant type; and whereinthe second dopant type is p-type.
 32. The semiconductor construction ofclaim 23 wherein the isolation region mass has a shape comprising a pairof opposing sidewalls; the construction further comprising a pair ofspacers along the opposing sidewalls; the two of the source/drainregions extending under the spacers.
 33. A method of forming anisolation region associated with a semiconductor construction,comprising: providing a semiconductive material substrate; forming aninsulative material over the semiconductive material substrate; forminga doped semiconductive material over the insulative material, the dopedsemiconductive being directly over a segment of the semiconductivematerial substrate, the doped semiconductive material having a firsttype majority dopant therein; forming a pair of conductively-dopeddiffusion regions within the semiconductive material adjacent thesegment, and spaced from one another by at least a portion of thesegment; the conductively-doped diffusion regions having a second typemajority dopant therein; one of the first and second types being n-typeand the other being p-type; providing an electrical ground associatedwith the substrate; and electrically connecting the doped semiconductivematerial to the electrical ground.
 34. The method of claim 33 whereinthe first type is n-type.
 35. The method of claim 33 wherein the firsttype is p-type.
 36. The method of claim 33 wherein more than 99% of thedopant in the doped semiconductive material is the first type; andwherein the first type is n-type.
 37. The method of claim 33 whereinmore than 99% of the dopant in the doped semiconductive material is thefirst type; and wherein the first type is p-type.
 38. The method ofclaim 33 wherein less than 99% of the dopant in the doped semiconductivematerial is the first type; and wherein the first type is n-type. 39.The method of claim 33 wherein less than 99% of the dopant in the dopedsemiconductive material is the first type; and wherein the first type isp-type.
 40. The method of claim 33 further comprising: initially dopingthe doped semiconductive material with second type dopant; andsubsequently counter-doping the doped semiconductive material withsufficient first type dopant to form the first type majority dopedsemiconductive material.
 41. The method of claim 40 wherein the initialdoping of the doped semiconductive material with second type dopantcomprises forming the doped semiconductive material to be in situ dopedwith the second type dopant.
 42. The method of claim 40 wherein theinitial doping of the doped semiconductive material with second typedopant comprises implanting second type dopant into the semiconductivematerial.
 43. The method of claim 33 wherein the semiconductive materialsubstrate comprises monocrystalline silicon.
 44. The method of claim 33wherein the insulative material comprises silicon dioxide.
 45. Themethod of claim 33 wherein the doped semiconductive material comprisesdoped polycrystalline silicon.
 46. The method of claim 33 wherein thedoped semiconductive material has a shape comprising a pair of opposingsidewalls; the method further comprising forming a pair of spacers alongthe opposing sidewalls, and wherein the conductively-doped diffusionregions extend under the spacers.
 47. A method of forming asemiconductor construction comprising forming a pair of transistorconstructions and an isolation region, wherein the transistorconstructions are electrically separated from one another by theisolation region, and wherein: each of the transistor constructionscomprises a transistor gate between a pair of source/drain regions; thetransistor gates comprising a first semiconductive material conductivelydoped to a first dopant type; and the source/drain regions comprising asecond semiconductive material conductively doped to the first dopanttype; the isolation region comprises a mass between two of thesource/drain regions; the isolation region mass comprises the firstsemiconductive material conductively doped to a second dopant type; andone of the first and second dopant types is n-type and the other isp-type.
 48. The method of claim 47 further comprising: initially dopingthe first semiconductive material of the isolation region mass withfirst type dopant; and subsequently counter-doping the firstsemiconductive material of the isolation region mass with sufficientsecond type dopant to form the second type doped first semiconductivematerial of the isolation region mass.
 49. The method of claim 48wherein the initial doping of the first semiconductive material of theisolation region mass comprises forming the first semiconductivematerial to be in situ doped with the first type dopant.
 50. The methodof claim 48 wherein the initial doping of the first semiconductivematerial of the isolation region mass comprises implanting first typedopant into the first semiconductive material of the isolation regionmass.
 51. The method of claim 48 wherein the initial doping of the firstsemiconductive material of the isolation region mass occurssimultaneously with doping of the first semiconductive material of thetransistor gates.
 52. The method of claim 47 wherein the isolationregion mass is formed over a first region of a semiconductor substrate,and wherein the transistor gates of the pair of transistor constructionsare formed over second and third regions of the semiconductor substrate,the method further comprising: simultaneously implanting dopant into thefirst, second and third regions of the semiconductor substrate prior toforming the isolation region mass and the transistor gates.
 53. Themethod of claim 52 wherein the semiconductor substrate comprisesmonocrystalline silicon, and wherein the source/drain regions arediffusion regions formed within the monocrystalline silicon.
 54. Themethod of claim 47 wherein the isolation region mass is formed over afirst region of a semiconductor substrate, and wherein the transistorgates of the pair of transistor constructions are formed over second andthird regions of the semiconductor substrate, the method furthercomprising: forming an insulative material over the semiconductorsubstrate; forming the isolation region mass and the transistor gatesover the insulative material; and simultaneously implanting dopantthrough the insulative material and into the first, second and thirdregions of the semiconductor substrate prior to forming the isolationregion mass and the transistor gates.
 55. The method of claim 54 whereinthe semiconductor substrate comprises monocrystalline silicon, andwherein the source/drain regions are diffusion regions formed within themonocrystalline silicon.
 56. The method of claim 47 wherein the two ofthe source/drain regions extend under the isolation region mass.
 57. Themethod of claim 47 wherein the transistor gates and isolation regionmass are formed over a monocrystalline silicon substrate.
 58. The methodof claim 47 wherein the first type is n-type.
 59. The method of claim 47wherein the first type is p-type.
 60. The method of claim 47 whereinmore than 99% of the dopant in the isolation region mass is the seconddopant type; and wherein the second dopant type is n-type.
 61. Themethod of claim 47 wherein more than 99% of the dopant in the isolationregion mass is the second dopant type; and wherein the second dopanttype is p-type.
 62. The method of claim 47 wherein less than 99% of thedopant in the isolation region mass is the second dopant type; andwherein the second dopant type is n-type.
 63. The method of claim 47wherein less than 99% of the dopant in the isolation region mass is thesecond dopant type; and wherein the second dopant type is p-type. 64.The method of claim 47 wherein the isolation region mass has a shapecomprising a pair of opposing sidewalls; the method further comprisingforming a pair of spacers along the opposing sidewalls, and wherein thetwo of the source/drain regions extend under the spacers.
 65. A methodof forming a semiconductor construction comprising: providing asemiconductor substrate; forming a pair of first transistorconstructions over a first region of the semiconductor substrate; eachof the first transistor constructions comprising a first transistor gatebetween a pair of first source/drain regions; the first transistor gatesand first source/drain regions comprising first-type conductively dopedregions of semiconductive material; forming at least one secondtransistor construction over a second region of the semiconductorsubstrate; the second transistor construction comprising a secondtransistor gate between a pair of second source/drain regions; thesecond transistor gate and second source/drain regions comprisingsecond-type conductively doped regions of semiconductive material;forming an isolation region between the pair of first transistorconstructions; the isolation comprising a mass between two of the firstsource/drain regions; the isolation region mass comprising a second-typeconductively doped region of semiconductive material; one of the firstand second dopant types being n-type and the other being p-type; andwherein second-type dopant is simultaneously implanted into theisolation region mass and the second transistor gate.
 66. The method ofclaim 65 further comprising: providing an electrical ground associatedwith the semiconductor substrate; and electrically connecting theconductively doped region of semiconductive material of the isolationregion mass with the electrical ground.
 67. The method of claim 65wherein the first type is n-type.
 68. The method of claim 65 wherein thefirst type is p-type.
 69. The method of claim 65 wherein thesemiconductive material substrate comprises monocrystalline silicon. 70.The method of claim 65 wherein the first type dopant is simultaneouslyimplanted into the isolation region mass and the first transistor gates,and wherein the concentration of the second type dopant in the isolationregion mass is greater than the concentration of the first type dopantin the isolation region mass.